The present invention pertains to the field of semiconductor design verification. More specifically, an embodiment of the present invention relates to a method and apparatus for determining equivalence of integrated circuit device designs.
Advances in semiconductor technology have led to substantial increases in gate count for integrated circuit devices such as Application Specific Integrated Circuit (ASIC) devices. This has significantly increased the run time for semiconductor design verification processes and in particular, equivalency checking processes.
Equivalence checking during verification uses either flat processes or hierarchical processes. Flat verification processes consider the design as a whole and do not consider heirarchical boundaries at all. Flat verification processes have a relatively quick setup process. However, with large design sizes, memory capacities are strained, impacting whether the design completes verification. In addition, extracted logic cone sizes can become unyieldingly large, leading to longer run times and indeterminate or hard verifications. This consumes valuable hardware, software and human resources. Moreover, as devices continue to be more complex and as gate counts continue to increase the time demands of flat verification processes will continue to worsen.
Hierarchical verification processes partition a design hierarchically into functional blocks. A determination is then made as to whether the implementation design implements all of the functional blocks of the reference design. This simplifies verification by controlling cone size and complexity, resulting in substantial performance improvements over flat verification processes. In addition, hierarchical verification processes require less memory because they verify one functional block at a time.
However, traditional hierarchical verification may require complex setup information or simply fail to prove equivalence, producing a xe2x80x9cfalse negativexe2x80x9d result. This is due to changes that blocks undergo during the design process. For example, boundary optimization pushes logic into other levels of hierarchy, which causes verification failures unless the differences are accounted for. Block name changes throughout the design flow can adversely affect module name mapping. Clock tree insertion with clock lines that cross hierarchical boundaries cause unmatched clock pins, producing mapping problems.
When failures occur in traditional hierarchical verification, the failures must then be debugged to determine whether the designs are in fact equivalent if their complete context is considered. In some hierarchical processes, when failures occur, the results of the hierarchical verification processes are analyzed by flattening out the design where the failure is found. However this often does not provide sufficient information to determine equivalence. Moreover, in some cases, the design is flattened completely and verification must be run in flat mode, causing loss of the advantages of hierarchical verification.
What is needed is a method and apparatus that provides quick analysis and verification of a semiconductor design. In addition, a method and apparatus is needed for determining equivalence of integrated circuit designs that does not produce false negative results.
The present invention includes an equivalence checker that gives quick analysis and verification of a semiconductor design. In addition, the method and apparatus of the present invention allows for determining equivalence of integrated circuit device designs and does not produce false negative results.
A method for determining equivalence between two integrated circuit device designs is disclosed in which functional blocks within a first integrated circuit design (the reference design) are matched with functional blocks in a second integrated circuit design (the implementation design) to determine compare points that are matched. In one embodiment, only registers, top-level primary outputs and pins at hierarchical boundaries are compared and matched. However, alternatively, other points could be compared.
During verification, the entire designs are considered (not individual blocks) but cut points are inserted at hierarchical pins that are matched. In one embodiment, each integrated circuit design is divided into collections of logic cones.
As each design is traversed, the cones are flattened such that a flat copy of both the reference design and the implementation design are obtained (that include the inserted cut points). In the present embodiment, cut points are not inserted at compare points that are determined to be constant.
The flat copies of the reference design and the implementation design are then compared to determine equivalence. In the present embodiment, equivalence is determined by creating a miter and solving the miter to determine whether the reference design is equivalent to the implementation design. In the present embodiment, the equivalence checker evaluates whether the logic function at a given compare point in one design is equivalent to the matching compare point in the other design as indicated by the inserted cut points.
In one embodiment of the present invention, when the comparison determines that the reference design and the implementation design are not equivalent, some of the cut points are selectively removed and the two designs are again compared. This process is repeated, continuing to remove cut points and compare designs, until the comparison indicates that the two integrated circuit device designs are equivalent, or no cut points remain.
The method and apparatus of the present invention allows for comparisons of versions of the design, both register transfer level to gate level, and gate level to gate level. Verification can be performed throughout the design cycle to maintain complete functional equivalence during every stage of the process flow.
The method and apparatus of the present invention recognizes the complete function of compare points (registers and top-level primary outputs) as in traditional flat verification processes. This eliminates false-negative results without requiring the extensive setup of prior art hierarchical verification process. The method and apparatus of the present invention verifies every compare point considering its entire (flat) context; however, it also automatically limits the size and complexity of cones by selectively verifying matched hierarchical pin boundaries, when appropriate. The intelligent selection of hierarchical cut points results in performance levels similar to those of prior art hierarchical verification processes. However, the method and apparatus of the present invention gives accuracy and ease of setup of a traditional flat verification process.